Grid array packaging has become an outstanding technique of connecting semiconductor chips with a printed circuit board. This technology, known as a ball grid array (BGA) or chip size package (CSP), is designed to make connection with a printed circuit board (PCB) often called a "mother board" containing grid pads, and by placing solder balls or solder paste on these pads. This technology is described in the book "Ball Grid Array Technology" edited by John H. Lau and published by McGraw Hill in 1995. In the ball grid array package 20 schematically shown in FIG. 9 (and essentially in FIG. 1.37 of such book), circuits 4, 4 (metallizations) are formed on both sides of a substrate or base material A such as an insulative PCB. A semiconductor chip 6 is mounted on the first surface 1 of the substrate, and pad electrodes 5 are formed in a grid on a second surface 2 of the substrate. The electrical connections between the circuits 4 on first surface 1 and the semiconductor chip 6 mounted on that first surface are made by wire bonds 11, and the electrical connections between the circuits 4 (metallizations) on the first surface 1 and the circuits 4 (metallizations) on the opposite second surface 2 of the substrate are usually made by a copper plating 13 of through-holes 12 located on the edges of a ball grid array 15. The semiconductor chip 6 is encapsulated molded by a molding resin 7.
The conventional BGA structure shown in FIG. 9 has the following problems. Firstly, since all electrical pads and area grid array pads, are routed out to the external edges, routing becomes extremely difficult when the semiconductor chip has a high density and a high pin count. Secondly, to insulate the circuits routing to the external edges and prevent flow of solder in the reflow soldering process, a solder resist process has had to be used to isolate the grid pads This process is relatively expensive. Thirdly, since the pad electrodes are planar, the solder ball or solder paste had small shear strength, and the solder balls were liable to delaminate. Fourthly, since the grid array package used a substrate from solid laminates such as a glass-epoxy laminate, reel-to-reel operation was impossible, and the mounting cost was expensive. To solve the first problem, a method of forming via-holes from the first surface to the second surface, and plating the internal surface of the via-holes (e.g. Japanese Open Patent, 7-74281) was developed. In this technology, the first problem is solved because the pad electrode is directly connected electrically to the circuit on the first surface.
The conventional ball grid array packages and their manufacturing methods required traces routing to the external edges from each pad electrode making grid rows on the substrate. The conventional package had difficulty in routing to the external edges and, to insulate routing traces and to prevent flowing of solder balls during reflow soldering, solder resist was required, which made it very expensive. The solder ball had a flat structure, and had a small solder ball shear strength, and easily delaminated.
Another conventional technology, in which via holes are formed and connected by plating between the first layer on which the semiconductor chip is mounted and the internal via holes, has advantages of not routing to the external edges, but on the other hand, it was difficult to form pad electrodes on the second surface, which required solder mask surrounding the pads.
Technologies using a laser for the formation of printed circuit boards are used mainly to perforate via holes. The laser used here is either an excimer laser, a YAO laser, or an impact laser which is an improved carbon dioxide laser. The application of an excimer laser to the manufacturing printed circuit boards are described in Japanese Open Patent 5-136650, 5-152744, and 5-152748, and the application of impact laser to the manufacturing of printed circuit boards is described in "A Large Format Modified TEA CO2 Laser Based Process for Cost Effective Via Generation" (1994 International Conference on Multichip Modules, Apr. 13-15, 1994). Reference is also made to U.S. Pat. No. 3,838,984 (FIGS. 5-8), where via holes are formed through a sheet (12) with gold bumps being found on the same side of the sheet for connecting both a chip and for connecting the sheet to a substrate.